Processor Timing Elements
SimSANs defines 25 timing elements for Host/CHIP CPU (9), FC-2 Controller (6), Switch CPU (3), and Device Control Memory CPU (7). Each of them is associated with a program task, in which instructions are decoded and executed by referencing memory spaces and consuming CPU cycles. The following formula is used for timing a task:
TaskTime = INSTR_NUM x (CPU_CYL_INS + MEM_REF_INS x Mem_Clock / CPU_Clock) / (CPU_Clock x 1000000)
where:
TaskTime | : CPU time consuming (second) to fulfill a task |
CPU_Clock |
: Processor clock in MHz |
Mem_Clock |
: Memory clock in MHz |
INSTR_NUM |
: Number of processor instructions to fulfill the task |
CPU_CYL_INS |
: Number of processor cycles for decoding and execution of an instruction |
MEM_REF_INS |
: Number of memory references needed for an instruction |
The following table lists all of the 25 tasks as well as the targets they belong to. Note usually each Processor Timing File contains tasks associated with one target but it is possible to include tasks associated with different targets into a single file when multiple targets use the same processor. For example you can setup Pentium_III_733 for both Host and Array and include both targets' timing elements into the same processor's timing file, say, Pentium_III_733.ini. Several sample timing files (MyHostCpu.ini, MyChipCpu.ini, MyFcCtrl.ini, MyArrayCpu.ini, and MySwCpu.ini) are included in the Package for user's reference, of which MyHostCpu.ini also demonstrates how multiple targets use the same processor.
Processor Tasks
Task Name |
Target |
Description |
FC4_IU_SEND |
Node (Host or CHIP) |
Issue FC4 IU |
FC4_IU_RECV |
Receive FC4 IU |
|
FCP_IU_SEND |
Issue FCP IU |
|
FCP_IU_RECV |
Receive FCP IU |
|
CRE_IT_PATH |
Create Initiator-Target Path |
|
RMV_IT_PATH |
Remove Initiator-Target Path |
|
INI_SCSI_IO |
Initiate SCSI IO |
|
INI_SCSI_SIO |
Initiate SCSI SubIO |
|
COM_SCSI_IO |
Conclude SCSI IO |
|
FC_SEQ_SEG |
FC_Ports |
FC Sequence segmentation |
FC_FRM_TXU |
Sending Frame updates ESB |
|
FC_FRM_RXU |
Receiving Frame updates ESB |
|
FC_SEQ_ASM |
FC Sequence assembly |
|
FC4_IU_SEND |
Issue FC4 IU, for FC-4 Controller in Switch Port |
|
FC4_IU_RECV |
Receive FC4 IU, for FC-4 Controller in Switch Port |
|
PER_CCH_IDX |
Array | Per-Cache block indexing |
COM_PND_BLK |
Complete a pending block and request/update Cache space |
|
SCSI_WR_SEG |
WRITE IO segmentation |
|
SCSI_RD_SEG |
READ IO segmentation |
|
RMV_LUN_IO |
Remove LUN IO due to IT_Path unavailable |
|
COM_BLK_WR |
Complete block write and update the Cache |
|
COM_BLK_RD |
Complete block read and update the Cache |
|
FRM_FWD |
Switch |
Lookup routing table and forward Frames |
NS_ZONE |
Naming and Zoning services |
|
RT_BULD |
Path selection and routing table building |
This page was last updated 2003.10.15