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Internal Switched Fabric
The core of the Internal Switched Fabric (CSW Fabric) is the
Cache Switch (CSW),
which creates the data transfer channel between
CHIP and CtrlMemCch, and between
ACP and CtrlMemCch - Note there's no direct
channel between CHIP and ACP. Each CSW has a
Bus Selector installed to exchange data with
CtrlMemCch through the least-congested channel.
Simplex modules are used to
create bus channels and perform bus arbitration. Three kinds of
buses are setup: Memory Bus (M),
CHIP Bus (C), and ACP Bus (A).
Following figure shows an example CSW Fabric with two CSWs
installed connecting with CtrlMemCch, two CHIPs, and two ACPs.
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Cache Switch (CSW)
Four types of data go through Cache Switches: Physical Block READ data (from ACP to CtrlMemCch), Physical Block WRITE data (from CtrlMemCch to ACP), SCSI DATA_OUT action (DATA_OUT_RECVD) from CHIP to CtrlMemCch, and SCSI DATA_IN action (SEND_DATA_IN) from CtrlMemCch to CHIP. Although CSW is a specially designed crossbar switch there is no direct connection path between CHIP and ACP. Multiple CSWs can be configured, each of which may setup multiple bus links with processor (CHIP, ACP, or CtrlMemCch), take the above picture for an example, each CSW has two paths to CHIP, two paths to ACP, and three paths to CtrlMemCch. Multiple-path connection can be able to  accommodate multiple simultaneous IOs, and  realize non-blocking data transfer through the selection of least-congested path.
Simplex module is used to model internal Disk Array buses including CHIP buses, ACP buses, and Memory buses. Different from the serial data communication, the bus uses parallel communication, in which the bus width of data occupies the whole bus and will not release it until they arrive at the destination. It is obvious that the bus communication is one-way or simplex communication. Simplex module has a built-in queue, which buffers data from CHIPs, ACPs, or CtrlMemCch on a first-in first-out basis. Whenever the bus is freed, a data will be popped out, and Simplex locks the whole bus and transfers the data. The busClock and busWidth can be customized by user for each bus before running a simulation. For example, for each CHIP, we can setup 2 buses with 32-bit busWidth and 100MHz busClock, i.e., a total 800MBps data transfer rate, which should be enough to accommodate the maximum traffic requirements by four 2G Fibre Channel links if each CHIP installs four 2G HBAs.
This page was last updated 2003.10.15